Typical of integrated semiconductor devices such as DRAMs, SRAMs, etc. is the desire to increase integration while decreasing the power supply voltage. To accomplish this, the threshold voltage (e.g., the gate-to-source voltage) to turn on the large number of MOS transistors included in such integrated circuit devices has been decreased. However, a reduction of the threshold voltage of the MOS transistors corresponding to the power supply voltage may increase the sub-threshold leakage current of the MOS transistors. The sub-threshold leakage current may be thought as the current leaking through the MOS transistor when the MOS transistor is meant to be in an off state.
This leakage current problem is particularly noticeable with respect to the CMOS inverter chains included in the integrated semiconductor devices. Many of the circuit elements in an integrated semiconductor device include one or more CMOS inverter chains. To combat this sub-threshold leakage current, the integrated circuit device may be operated in a standby mode or active mode. In the active mode, the circuit elements operate at their normal high speed. In the standby mode, each circuit element operates in a way to reduce leakage current, but also at a reduced operating speed. For example, one or more transistors in the CMOS inverter chains of each circuit element may have their bulk biases changed in the standby mode to reduce the sub-threshold leakage current.